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ds007601-z8x0499 1 p reliminary p roduct s pecification z86c34/c35/c36 z86c44/c45/c46 cmos z8 ? mcu s with asci uart o ffer e fficient , c ost -e ffective d esign f lexibility features ? 28-pin dip, 28-pin soic and plcc packages (c34, c35, c36) ? 40-pin dip, 44-pin plcc and qfp packages (c44, c45, c46) ? 3.0- to 5.5-volt operating range ? clock free watch-dog timer (wdt) reset ? operating temperature ranges: standard: 0 c to 70 c extended: C40 c to +105 c ? expanded register file (erf) ? full-duplex uart (asci) ? dedicated 16-bit baud rate generator ? 32 input/output lines (c44/c45/c46) 24 input/output lines (c34/c35/c36) ? vectored, prioritized interrupts with programmable po- larity ? two analog comparators ? two programmable 8-bit counter/timers, each with two 6-bit programmable prescaler ? watch-dog timer (wdt)/power-on reset (por) ? on-chip oscillator that accepts a crystal, ceramic res- onator, lc, rc, or external clock ? ram and rom protect ? optional 32-khz oscillator general description zilogs z8 ? mcu single-chip family now includes the z86c34/c35/c36/c44/c45/c46 product line, featuring en- hanced wake-up circuitry, programmable watch-dog tim- ers ( wdt ), and low-noise/emi options. each of the new en- hancements to the z8 offer a more efficient, cost-effective design and provide the user with increased design flexibility over the standard z8 microcontroller core. the low-power consumption cmos microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/out- put bit manipulation capabilities, and easy hardware/soft- ware system expansion. the z8 subfamily features an expanded register file ( erf ) to allow access to register-mapped peripheral and i/o cir- cuits. four basic address spaces are available to support this wide range of configurations: program memory, register file, data memory, and erf . the register file is composed of 236/237 bytes of general-purpose registers, four i/o port registers, and 15 control and status registers. the erf con- sists of twelve control registers. for applications demanding powerful i/o capabilities, the z86c34/c35/c36 offers 24 pins, and the z86c44/c45/c46 offers 32 pins dedicated to input and output. these lines are device rom (kb) ram* (bytes) speed (mhz) z86c34 16 237 16 Z86C35 32 237 16 z86c36 64 237 16 z86c44 16 236 16 z86c45 32 236 16 z86c46 64 236 16 note: *general-purpose.
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 2 p r e l i m i n a r y ds007601-z8x0499 general description (continued) configurable under software control to provide timing, sta- tus signals, parallel i/o with or without handshake, and ad- dress/data bus for interfacing external memory. to unburden the system from coping with real-time tasks such as counting/timing and data communication, the z8 offer two on-chip counter/timers with a large number of user-selectable modes. with rom/romless selectivity, the z86c44/c45/c46 provide both external memory and preprogrammed rom, which enables this z8 ? mcu to be used in high-volume ap- plications, or where code flexibility is required. note: all signals with an overline are active low. for exam- ple, b/ w , for which word is active low, and b /w, for which byte is active low. power connections follow these conventional descriptions: connection circuit device power v cc v dd ground gnd v ss figure 1. functional block diagram port 3 counter/ timers (2) interrupt control two analog comparators port 2 i/o (bit programmable) alu flag register pointer register file machine timing & inst. control reset wdt, por program memory program counter v gnd xtal 44 port 0 as ds r/w reset output input port 1 8 address or i/o (nibble programmable) address/data or i/o (byte programmable) (c44/c45/c46 only) (c44/c45/c46 only) cc full-duplex uart 16-bit baud rate generator
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 3 pin description figure 2. 28-pin dip/soic pin con?guration p25 p26 p27 p04 p05 p06 p07 v cc xtal2 xtal1 p31 p32 p33 p34 p24 p23 p22 p21 p20 p03 gnd p02 p01 p00 p30 p36 p37 p35 28 z86c34/c35/c36 1 14 15 figure 3. 28-pin plcc pin con?guration 25 19 5 11 18 12 26 4 z86c34/c35/c36 1 p21 p20 p03 gnd p02 p01 p00 p05 p06 p07 v cc xtal2 xtal1 p31 p04 p27 p26 p25 p24 p23 p22 p32 p33 p34 p35 p37 p36 p30 table 1. 28-pin dip/soic/plcc pin identi?cation pin # symbol function direction 1C3 p25C27 port 2, bits 5,6,7 in/output 4C7 p04C07 port 0, bits 4,5,6,7 in/output 8v cc power supply 9 xtal2 crystal oscillator output 10 xtal1 crystal oscillator input 11C13 p31C33 port 3, bits 1,2,3 fixed input 14C15 p34C35 port 3, bits 4,5 fixed output 16 p37 port 3, bit 7 fixed output 17 p36 port 3, bit 6 fixed output 18 p30 port 3, bit 0 fixed input 19C21 p00C02 port 0, bits 0,1,2 in/output 22 gnd ground 23 p03 port 0, bit 3 in/output 24C28 p20C24 port 2, bits 0,1,2,3,4 in/output
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 4 p r e l i m i n a r y ds007601-z8x0499 pin description (continued) figure 4. 40-pin dip con?guration r/w p25 p26 p27 p04 p05 p06 p14 p15 p07 v cc p16 p17 xtal2 xtal1 p31 p32 p33 p34 as ds p24 p23 p22 p21 p20 p03 p13 p12 gnd p02 p11 p10 p01 p00 p30 p36 p37 p35 reset 40 z86c44/c45/c46 1 20 21 table 2. 40-pin dual-in-line package pin identi?cation pin # symbol function direction 1 r/w read/write output 2C4 p25C27 port 2, bits 5,6,7 in/output 5C7 p04C06 port 0, bits 4,5,6 in/output 8C9 p14C15 port 1, bits 4,5 in/output 10 p07 port 0, bit 7 in/output 11 v cc power supply 12C13 p16C17 port 1, bits 6,7 in/output 14 xtal2 crystal oscillator output 15 xtal1 crystal oscillator input 16C18 p31C33 port 3, bits 1,2,3 input 19 p34 port 3, bit 4 output 20 as address strobe output 21 reset reset input 22 p35 port 3, bit 5 output 23 p37 port 3, bit 7 output 24 p36 port 3, bit 6 output 25 p30 port 3, bit 0 input 26C27 p00C01 port 0, bit 0,1 in/output 28C29 p10C11 port 1, bit 0,1 in/output 30 p02 port 0, bit 2 in/output 31 gnd ground 32C33 p12C13 port 1, bit 2,3 in/output 34 p03 port 0, bit 3 in/output 35C39 p20C24 port 2, bit 0,1,2,3,4 in/output 40 ds data strobe output table 2. 40-pin dual-in-line package pin identi?cation pin # symbol function direction
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 5 figure 5. 44-pin plcc pin con?guration z86c44/c45/c46 7 17 p21 p22 p23 p24 ds nc r/w p25 p26 p27 p04 p30 p36 p37 p35 reset r/rl as p34 p33 p32 p31 p05 p06 p14 p15 p07 v cc v cc p16 p17 xtal2 xtal1 p20 p03 p13 p12 gnd gnd p02 p11 p10 p01 p00 1 28 18 40 39 29 6 table 3. 44-pin plcc pin identi?cation pin # symbol function direction 1C2 gnd ground 3C4 p12C13 port 1, bits 2,3 in/output 5 p03 port 0, bit 3 in/output 6C10 p20C24 port 2, bits 0,1,2,3,4 in/output 11 ds data strobe output 12 nc not connected 13 r/w read/write output 14C16 p25C27 port 2, bits 5,6,7 in/output 17C19 p04C06 port 0, bits 4,5,6 in/output 20C21 p14C15 port 1, bits 4,5 in/output 22 p07 port 0, bit 7 in/output 23C24 v cc power supply 25C26 p16C17 port 1, bits 6,7 in/output 27 xtal2 crystal oscillator output 28 xtal1 crystal oscillator input 29C31 p31C33 port 3, bits 1,2,3 input 32 p34 port 3, bit 4 output 33 as address strobe output 34 r/rl rom/romless control input 35 reset reset input 36 p35 port 3, bit 5 output 37 p37 port 3, bit 7 output 38 p36 port 3, bit 6 output 39 p30 port 3, bit 0 input 40C41 p00C01 port 0, bits 0,1 in/output 42C43 p10C11 port 1, bits 0,1 in/output 44 p02 port 0, bit 2 in/output table 3. 44-pin plcc pin identi?cation pin # symbol function direction
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 6 p r e l i m i n a r y ds007601-z8x0499 pin description (continued) figure 6. 44-pin qfp pin con?guration 34 44 p21 p22 p23 p24 ds nc r/w p25 p26 p27 p04 p30 p36 p37 p35 reset r/rl as p34 p33 p32 p31 p05 p06 p14 p15 p07 v cc v cc p16 p17 xtal2 xtal1 p20 p03 p13 p12 gnd gnd p02 p11 p10 p01 p00 1 23 33 z86c44/c45/c46 11 22 12 table 4. 44-pin qfp pin identi?cation pin # symbol function direction 1C2 p05C06 port 0, bits 5,6 in/output 3C4 p14C15 port 1, bits 4,5 in/output 5 p07 port 0, bit 7 in/output 6C7 v cc power supply 8C9 p16C17 port 1 bits 6,7 in/output 10 xtal2 crystal oscillator output 11 xtal1 crystal oscillator input 12C14 p31C33 port 3, bits 1,2,3 input 15 p34 port 3, bit 4 output 16 as address strobe output 17 r/rl rom/romless control input 18 reset reset input 19 p35 port 3, bit 5 output 20 p37 port 3, bit 7 output 21 p36 port 3, bit 6 output 22 p30 port 3, bit 0 input 23C24 p00C01 port 0, bits 0,1 in/output 25C26 p10C11 port 1, bits 0,1 in/output 27 p02 port 0, bit 2 in/output 28C29 gnd ground 30C31 p12C13 port 1, bits 2,3 in/output 32 p03 port 0, bit 3 in/output 33C37 p20C24 port 2, bits 0,1,2,3,4 in/output 38 ds data strobe output 39 nc not connected 40 r/w read/write output table 4. 44-pin qfp pin identi?cation pin # symbol function direction
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 7 absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this rating is a stress rating only. functional operation of the de- vice at any condition above those indicated in the opera- tional sections of these specifications is not implied. expo- sure to absolute maximum rating conditions for an extended period may affect device reliability. total power dissipation should not exceed 1.21 w for the package. power dissipation is calculated as follows: parameter min max units notes ambient temperature under bias C40 +105 c storage temperature C65 +150 c voltage on any pin with respect to v ss C0.6 +7 v 1 voltage on v dd pin with respect to v ss C0.3 +7 v voltage on xtal1 and reset pins with respect to v ss C0.6 v dd +1 v 2 total power dissipation 1.21 w maximum allowable current out of v ss 220 ma maximum allowable current into v dd 180 ma maximum allowable current into an input pin C600 +600 a 3 maximum allowable current into an open-drain pin C600 +600 a 4 maximum allowable output current sunk by any i/o pin 25 ma maximum allowable output current sourced by any i/o pin 25 ma notes: 1. applies to all pins except xtal pins and where otherwise noted. 2. there is no input protection diode from pin to v dd and current into pin is limited to 600 a. 3. excludes xtal pins. 4. device pin is not at an output low state. total power dissipation = v dd x [i dd C (sum of i oh ), + sum of [(v dd C v oh ) x i oh ] + sum of (v ol x i ol )
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 8 p r e l i m i n a r y ds007601-z8x0499 standard test conditions the characteristics listed in following pages apply for stan- dard test conditions as noted. all voltages are referenced to gnd . positive current flows into the referenced pin (see figure 7.) capacitance t a = 25oc, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins to gnd figure 7. test load diagram from output under test 150 pf parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 9 dc electrical characteristics table 5. dc characteristics t a = 0c to +70c t a = C40c to +105c sym parameter v cc 1 min max min max typical 2 @25c units conditions notes v ch clock input high voltage 3.0v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 1.8 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 2.6 v driven by external clock generator v cl clock input low voltage 3.0v gndC0.3 0.2 v cc gndC0.3 0.2 v cc 1.2 v driven by external clock generator 5.5v gndC0.3 0.2 v cc gndC0.3 0.2 v cc 2.1 v driven by external clock generator v ih input high voltage 3.0v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 1.8 v 5.5v 0.7 v cc v cc +0.3 0.7 v cc v cc +0.3 2.6 v v il input low voltage 3.0v gndC0.3 0.2 v cc gndC0.3 0.2 v cc 1.1 v 5.5v gndC0.3 0.2 v cc gndC0.3 0.2 v cc 1.6 v v oh output high voltage (low-emi mode) 3.0v v cc C0.4 v cc C0.4 3.1 v i oh = C0.5 ma 5.0v v cc C0.4 v cc C0.4 4.8 v i oh = C0.5 ma v oh1 output high voltage 3.0v v cc C0.4 v cc C0.4 3.1 v i oh = C2.0 ma 3 5.5v v cc C0.4 v cc C0.4 4.8 v i oh = C2.0 ma 3 v ol output low voltage (low-emi mode) 3.0v 0.6 0.6 0.2 v i ol = 1.0 ma 5.0v 0.4 0.4 0.1 v i ol = 1.0 ma v ol1 output low voltage 3.0v 0.6 0.6 0.2 v i ol = +4.0 ma 3 5.5v 0.4 0.4 0.1 v i ol = +4.0 ma 3 notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typicals are at v cc = 5.0v and 3.3v. 3. standard mode (not low emi). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins floating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when xtal 1 is clock-driven and xtal2 is floating. 9. 0oc to 70oc (standard temperature). 10. auto latch (mask option) selected. 11. the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. 12. C40?c to 150?c (extended temperature).
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 10 p r e l i m i n a r y ds007601-z8x0499 dc electrical characteristics (continued) v ol2 output low voltage 3.0v 1.2 1.2 0.3 v i ol = +6 ma 3 5.5v 1.2 1.2 0.4 v i ol = +12 ma 3 v rh reset input high voltage 3.0v .8 v cc v cc .8 v cc v cc 1.8 v 4 5.5v .8 v cc v cc .8 v cc v cc 2.6 v 4 v rl reset input low voltage 3.0v gndC0.3 0.2 v cc gndC0.3 0.2 v cc 1.1 v 4 5.5v gndC0.3 0.2 v cc gndC0.3 0.2 v cc 1.6 v 4 v olr reset output low voltage 3.0v 0.6 0.6 0.3 v i ol = +1.0 ma 4 5.5v 0.6 0.6 0.3 v i ol = +1.0 ma 4 v offset comparator input offset voltage 3.0v 25 25 10 mv 5 5.5v 25 25 10 mv 5 i il input leakage 3.0v C1 2 C1 2 0.004 a v in = 0v, v cc 5.5v C1 2 C1 2 0.004 a v in = 0v, v cc i ol output leakage 3.0v C1 1 C1 2 0.004 a v in = 0v, v cc 5.5v C1 1 C1 2 0.004 a v in = 0v, v cc iir reset input current 3.0v C20 C130 C18 C130 C60 a 5.5v C20 C180 C18 C180 C85 a i cc supply current 3.0v 20 20 7 ma @ 16 mhz 6 5.5v 25 25 20 ma @ 16 mhz 6 3.0v 15 15 5 ma @ 12 mhz 6 5.5v 20 20 15 ma @ 12 mhz 6 table 5. dc characteristics (continued) t a = 0c to +70c t a = C40c to +105c sym parameter v cc 1 min max min max typical 2 @25c units conditions notes notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typicals are at v cc = 5.0v and 3.3v. 3. standard mode (not low emi). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins floating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when xtal 1 is clock-driven and xtal2 is floating. 9. 0oc to 70oc (standard temperature). 10. auto latch (mask option) selected. 11. the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. 12. C40?c to 150?c (extended temperature).
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 11 i cc1 standby current (halt mode) 3.0v 4.5 4.5 2.0 ma v in = 0v, v cc @ 16 mhz 6 5.5v 8 8 3.7 ma v in = 0v, v cc @ 16 mhz 6 3.0v 3.4 3.4 1.5 ma clock divide- by-16 @ 16 mhz 6 5.5v 7.0 7.0 2.9 ma clock divide- by-16 @ 16 mhz 6 i cc2 standby current (stop mode) 3.0v 8 8 2 a v in = 0v, v cc wdt is not running 7,8 5.5v 10 10 4 a v in = 0v, v cc wdt is not running 7,8 3.0v 500 600 310 a v in = 0v, v cc wdt is running 7,8,9 5.5v 800 1000 600 a v in = 0v, v cc wdt is running 7,8,9 v icr input common mode voltage range 3.0v 0 v cc C1.0v 0 v cc C1.5v v 5 5.5v 0 v cc C1.0v 0 v cc C1.5v v 5 i all auto latch low current 3.0v 0.7 8 0.7 10 3 a 0v < v in < v cc 10 5.5v 1.4 15 1.4 20 5 a 0v < v in < v cc 10 i alh auto latch high current 3.0v C0.6 C5 C0.6 C7 C3 a 0v < v in < v cc 10 5.5v C1.0 C8 C1.0 C10 C6 a 0v < v in < v cc 10 table 5. dc characteristics (continued) t a = 0c to +70c t a = C40c to +105c sym parameter v cc 1 min max min max typical 2 @25c units conditions notes notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typicals are at v cc = 5.0v and 3.3v. 3. standard mode (not low emi). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins floating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when xtal 1 is clock-driven and xtal2 is floating. 9. 0oc to 70oc (standard temperature). 10. auto latch (mask option) selected. 11. the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. 12. C40?c to 150?c (extended temperature).
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 12 p r e l i m i n a r y ds007601-z8x0499 dc electrical characteristics (continued) v lv v cc low voltage protection voltage 2.0 3.3 2.8 v 4 mhz max int. clk freq. 11,12 2.2 3.1 2.8 6 mhz max int. clk freq. 9,11 table 5. dc characteristics (continued) t a = 0c to +70c t a = C40c to +105c sym parameter v cc 1 min max min max typical 2 @25c units conditions notes notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typicals are at v cc = 5.0v and 3.3v. 3. standard mode (not low emi). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins floating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when xtal 1 is clock-driven and xtal2 is floating. 9. 0oc to 70oc (standard temperature). 10. auto latch (mask option) selected. 11. the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. 12. C40?c to 150?c (extended temperature).
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 13 ac electrical characteristics external i/o or memory read and write timing figure 8. external i/o or memory read and write timing r/w 9 12 18 3 16 13 4 5 8 11 6 17 10 15 7 14 2 1 port 0, dm port 1 as ds (read) port1 ds (write) d7?0 in d7?0 out a7?0 a7?0 19 20
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 14 p r e l i m i n a r y ds007601-z8x0499 ac electrical characteristics (continued) table 6. external i/o or memory read and write timing (c44/c45/c46 only) (sclk/tclk = xtal/2) t a = C0oc to 70oc t a = C40oc to +105oc 12 mhz 16 mhz 12 mhz 16 mhz no symbol parameter v cc 1 min max min max min max min max units notes 1 tda(as) address valid to as rise delay 3.0 35 25 35 25 ns 2 5.5 35 25 35 25 ns 2 2 tdas(a) as rise to address float delay 3.0 45 35 45 35 ns 2 5.5 45 35 45 35 ns 2 3 tdas(dr) as rise to read data reqd valid 3.0 250 180 250 180 ns 2,3 5.5 250 180 250 180 ns 2 4twas as low width 3.0 55 40 55 40 ns 2 5.5 55 40 55 40 ns 2 5 tdas(ds) address float to ds fall 3.00000ns 5.50000ns 6 twdsr ds (read) low width 3.0 200 135 200 135 ns 2,3 5.5 200 135 200 135 ns 2,3 7 twdsw ds (write) low width 3.0 110 80 110 80 ns 2,3 5.5 110 80 110 80 ns 2,3 8 tddsr(dr) ds fall to read data reqd valid 3.0 150 75 150 75 ns 2,3 5.5 150 75 150 75 ns 2,3 9 thdr(ds) read data to ds rise hold time 3.00000ns2 5.50000ns2 10 tdds(a) ds rise to address active delay 3.0 45 50 45 50 ns 2 5.5 55 50 55 50 ns 2 11 tdds(as) ds rise to as fall delay 3.0 30 35 30 35 ns 2 5.5 45 35 45 55 ns 2 12 tdr/w(as) r/w valid to as rise delay 3.0 45 25 45 25 ns 2 5.5 45 25 45 25 ns 2 13 tdds(r/w) ds rise to r/w not valid 3.0 45 35 45 35 ns 2 5.5 45 35 45 35 ns 2 14 tddw(dsw) write data valid to ds fall (write) delay 3.0 55 25 55 25 ns 2 5.5 55 25 55 25 ns 2 15 tdds(dw) ds rise to write data not valid delay 3.0 45 35 45 35 ns 2 5.5 45 35 45 35 ns 2 16 tda(dr) address valid to read data reqd valid 3.0 310 230 310 230 ns 2,3 5.5 310 230 310 230 ns 2,3 notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing numbers provided are for minimum tpc. 3. when using extended memory timing add 2 tpc.
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 15 17 tdas(ds) as rise to ds fall delay 3.0 65 45 65 45 ns 2 5.5 65 45 65 45 ns 2 18 tddm(as) dm valid to as fall delay 3.0 35 30 35 30 ns 2 5.5 35 30 35 30 ns 2 19 tdds(dm) ds rise to dm valid delay 3.0 5.5 45 45 35 35 45 45 35 35 ns ns 2 2 20 thds(as) ds valid to address valid hold time 3.0 5.5 45 45 35 35 45 45 35 35 ns ns 2 2 table 6. external i/o or memory read and write timing (c44/c45/c46 only) (sclk/tclk = xtal/2) (continued) t a = C0oc to 70oc t a = C40oc to +105oc 12 mhz 16 mhz 12 mhz 16 mhz no symbol parameter v cc 1 min max min max min max min max units notes notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing numbers provided are for minimum tpc. 3. when using extended memory timing add 2 tpc.
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 16 p r e l i m i n a r y ds007601-z8x0499 ac electrical characteristics (continued) additional timing diagram figure 9. additional timing clock 1 3 4 8 2 2 3 tin irqn 6 5 7 7 11 clock setup 10 9 stop mode recovery source
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 17 table 7. additional timing (sclk/tclk = xtal/2) t a = 0oc to +70oc t a = C40oc to +105oc 12 mhz 16 mhz 12 mhz 16 mhz no symbol parameter v cc 1 min max min max min max min max units notes d1,d0 1 tpc input clock period 3.0v 83 dc 62.5 dc 83 dc 62.5 dc ns 2,3,4 5.5v 83 dc 62.5 dc 83 dc 62.5 dc ns 2,3,4 3.0v 250 dc 250 dc 250 dc 250 dc ns 2,3 5.5v 250 dc 250 dc 250 dc 250 dc ns 2,3 2 trc,tfc clock input rise & fall times 3.0v 15 15 15 15 ns 2,3 5.5v 15 15 15 15 ns 2,3 3 twc input clock width 3.0v 41 31 41 31 ns 2,3,4 5.5v 41 31 41 31 ns 2,3,4 3.0v 125 125 125 125 ns 2,3 5.5v 125 125 125 125 ns 2,3 4 twtinl timer input low width 3.0v 100 100 100 100 ns 2,3 5.5v 70 70 70 70 ns 2,3 5 twtinh timer input high width 3.0v 5tpc 5tpc 5tpc 5tpc 2,3 5.5v 5tpc 5tpc 5tpc 5tpc 2,3 6 tptin timer input period 3.0v 8tpc 8tpc 8tpc 8tpc 2,3 5.5v 8tpc 8tpc 8tpc 8tpc 2,3 7 trtin, tftin timer input rise & fall timer 3.0v 100 100 100 100 ns 2,3 5.5v 100 100 100 100 ns 2,3 8a twil int. request low time 3.0v 100 100 100 100 ns 2,3,5 5.5v 70 70 70 70 ns 2,3,5 8b twil int. request low time 3.0v 5tpc 5tpc 5tpc 5tpc 2,3,6 5.5v 5tpc 5tpc 5tpc 5tpc 2,3,6 9 twih int. request input high time 3.0v 5tpc 5tpc 5tpc 5tpc 2,3,5 5.5v 5tpc 5tpc 5tpc 5tpc 2,3,5 10 twsm stop-mode recovery width spec 3.0v 12 12 12 12 ns 7 5.5v 12 12 12 12 ns 7 11 tost oscillator startup time 3.0v 5tpc 5tpc 5tpc 5tpc 7,8 5.5v 5tpc 5tpc 5tpc 5tpc 7,8 notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0 . 3. smr d1 = 0. 4. maximum frequency for external xtal clock is 4 mhz when using low-emi oscillator mode pcon reg.d7 = 0. 5. interrupt request via port 3 (p31Cp33). 6. interrupt request via port 3 (p30). 7. smrCd5 = 1, por stop mode delay is on. 8. for rc and lc oscillator, and for oscillator driven by clock driver. 9. register wdtmr.
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 18 p r e l i m i n a r y ds007601-z8x0499 ac electrical characteristics (continued) 12 twdt watch-dog timer delay timer before time-out 3.0v 7 7 7 7 ms 9 0,0 5.5v 3.5 3.5 3.5 3.5 ms 9 0,0 3.0v 14 14 14 14 ms 9 0,1 5.5v 7 7 7 7 ms 9 0,1 3.0v 28 28 28 28 ms 9 1,0 5.5v 14 14 14 14 ms 9 1,0 3.0v 112 112 112 112 ms 9 1,1 5.5v 56 56 56 56 ms 9 1,1 13 tpor power-on reset delay 3.0v 3 24 3 24 3 25 3 25 ms 5.5v 1.5 13 1.5 13 1 14 1 14 ms table 7. additional timing (sclk/tclk = xtal/2) (continued) t a = 0oc to +70oc t a = C40oc to +105oc 12 mhz 16 mhz 12 mhz 16 mhz no symbol parameter v cc 1 min max min max min max min max units notes d1,d0 notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0 . 3. smr d1 = 0. 4. maximum frequency for external xtal clock is 4 mhz when using low-emi oscillator mode pcon reg.d7 = 0. 5. interrupt request via port 3 (p31Cp33). 6. interrupt request via port 3 (p30). 7. smrCd5 = 1, por stop mode delay is on. 8. for rc and lc oscillator, and for oscillator driven by clock driver. 9. register wdtmr.
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 19 table 8. additional timing (divide-by-one mode, sclk/tclk = xtal) t a = 0oc to +70oc t a = 40oc to +105oc v cc 1 8 mhz 8 mhz no symbol parameter min max min max units notes 1 tpc input clock period 3.0v 250 dc 250 dc ns 2,3,4 5.5v 250 dc 250 dc ns 2,3,4 3.0v 125 dc 125 dc ns 2,3 5.5v 125 dc 125 dc ns 2,3 2 trc,tfc clock input rise & fall times 3.0v 25 25 ns 2,3 5.5v 25 25 ns 2,3 3 twc input clock width 3.0v 125 125 ns 2,3,4 5.5v 125 125 ns 2,3,4 3.0v 62 62 ns 2,3 5.5v 62 62 ns 2,3 4 twtinl timer input low width 3.0v 100 100 ns 2,3 5.5v 70 70 ns 2,3 5 twtinh timer input high width 3.0v 3tpc 3tpc 2,3 5.5v 3tpc 3tpc 2,3 6 tptin timer input period 3.0v 4tpc 4tpc 2,3 5.5v 4tpc 4tpc 2,3 7 trtin, tftin timer input rise & fall timer 3.0v 100 100 ns 2,3 5.5v 100 100 ns 2,3 8a twil int. request low time 3.0v 100 100 ns 2,3,5 5.5v 70 70 ns 2,3,5 8b twil int. request low time 3.0v 3tpc 3tpc 2,3,6 5.5v 3tpc 3tpc 2,3,6 9 twih int. request input high time 3.0v 3tpc 3tpc 2,3,5 5.5v 3tpc 2tpc 2,3,5 10 twsm stop-mode recovery width spec 3.0v 12 12 ns 7 5.5v 12 12 ns 7 11 tost oscillator startup time 3.0v 5tpc 5tpc 7,8 5.5v 5tpc 5tpc 7,8 notes: 1. the v cc voltage speci?cation of 3.0v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 3. smr d1 = 0. 4. maximum frequency for external xtal clock is 4 mhz when using low-emi oscillator mode pcon reg.d7 = 0. 5. interrupt request via port 3 (p31Cp33). 6. interrupt request via port 3 (p30). 7. smrCd5 = 1, por stop mode delay is on. 8. for rc and lc oscillator, and for oscillator driven by clock driver.
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 20 p r e l i m i n a r y ds007601-z8x0499 ac electrical characteristics (continued) handshake timing diagrams figure 10. input handshake timing data in 1 2 3 4 dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid 5 6 figure 11. output handshake timing data out dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 21 table 9. handshake timing 1 t a = 0c to +70c t a = C40c to +105c 12 mhz 16 mhz 12 mhz 16 mhz data direction no symbol parameter v cc 2 min max min max min max min max 1 tsdi(dav) data in setup time 3.0v 0 0 0 0 in 5.5v 0 0 0 0 in 2 thdi(rdy) data in hold time 3.0v 0 0 0 0 in 5.5v 0 0 0 0 in 3 twdav data available width 3.0v 155 155 155 155 in 5.5v 110 110 110 110 in 4 tddavi(rdy) dav fall to rdy fall delay 3.0v 0 0 0 0 in 5.5v 0000in 5 tddavid(rdy) dav out to dav fall delay 3.0v 120 120 120 120 in 5.5v 80 80 80 80 in 6 rdy0d(dav) rdy rise to dav fall delay 3.0v 0000 in 5.5v 0000 in 7 tdd0(dav) data out to dav fall delay 3.0v 42 31 42 31 out 5.5v 42 31 42 31 out 8 tddav0(rdy) dav fall to rdy fall delay 3.0v 0000 out 5.5v 0000 out 9 tdrdy0(dav) rdy fall to dav rise delay 3.0v 160 160 160 160 out 5.5v 115 115 115 115 out 10 twrdy rdy width 3.0v 110 110 110 110 out 5.5v 80 80 80 80 out 11 tdrdy0d(dav) rdy rise to dav fall delay 3.0v 110 110 110 110 out 5.5v 80 80 80 80 out note: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0 . 2. the v cc voltage specification of 3.0v guarantees 3.3v 0.3v. the v cc voltage specification of 5.5v guarantees 5.0v 0.5v.
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 22 p r e l i m i n a r y ds007601-z8x0499 pin functions r/ rl (input, active low). the rom/romless pin, when connected to gnd , disables the internal rom and forces the device to function as a romless z8. (not available for devices in the 28-pin package.) notes: when left unconnected or pulled high to v cc , the device functions normally as a z8 rom version. when using in rom mode in a high-emi (noisy) environment, the romless pins should be connected directly to v cc . ds (output, active low). data strobe is activated one time for each external memory transfer. for a read oper- ation, data must be available prior to the trailing edge of ds . for write operations, the falling edge of ds indicates that output data is valid. (not available for devices in the 28- pin package.) as (output, active low). address strobe is pulsed one time at the beginning of each machine cycle for external memory transfer. address output is from port 0/port 1 for all external programs. memory address transfers are valid at the trailing edge of as . under program control, as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write . (not available for de- vices in the 28-pin package.) xtal1 crystal 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc , or rc net- work, or an external single-phase clock to the on-chip os- cillator input. xtal2 crystal 2 (time-based output). this pin connects a parallel-resonant crystal, ceramic resonant, lc , or rc net- work to the on-chip oscillator output. r/ w (output, write low). the read/write signal is low when the z8 is writing to the external program or data memory. (not available for devices in the 28-pin package.)
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 23 port 0 (p00Cp07). port 0 is an 8-bit, bidirectional, cmos- compatible port. these eight i/o lines are configured under software control as a nibble i/o port ( p03Cp00 input/output and p07Cp04 input/output), or as an address port for inter- facing external memory. the input buffers are schmitt-trig- gered and nibble-programmed as outputs and can be glo- bally programmed as either push-pull or open-drain. low- emi output buffers can be globally programmed by the soft- ware. port 0 is placed under handshake control. in this con- figuration, port 3, lines p32 and p35 are used as the hand- shake control da v0 and rdy0 . handshake signal direction is dictated by the i/o direction (input or output) of port 0 of the upper nibble p04Cp07 . the lower nibble must indi- cate the same direction as the upper nibble. for external memory references, port 0 provides address bits a11Ca8 (lower nibble) or a15Ca8 (lower and upper nibble) depending on the required address space. if the ad- dress range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for addressing. if one or both nibbles are re- quired for i/o operation, they are configured by writing to the port 0 mode register. in romless mode, after a hardware reset , port 0 is con- figured as address lines a15Ca8 , and extended timing is set to accommodate slow memory access. the initialization routine can include reconfiguration to eliminate this ex- tended timing mode. (in rom mode, port 0 is defined as input after reset .) port 0 can be placed in a high-impedance state along with port 1, as , ds and r/w , allowing the z8 to share common re- sources in multiprocessor and dma applications (figure 12). figure 12. port 0 con?guration port 0 (i/o or a15?8) handshake controls dav0 and rdy0 (p32 and p35) z8 4 4 open-drain oe out in 1.5 2.3 hysteresis @ v = 5.0v pad pull-up transistor enable (mask option) auto latch (mask option) r 500k cc
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 24 p r e l i m i n a r y ds007601-z8x0499 pin functions (continued) port 1 (p17Cp10). port 1 is an 8-bit, bidirectional, cmos- compatible port (figure 13), with multiplexed address ( a7Ca0 ) and data ( d7Cd0 ) ports. for the rom device, these eight i/o lines are programmed as inputs or outputs, or can be configured under software control as an ad- dress/data port for interfacing external memory. the input buffers are schmitt-triggered and byte-programmed as out- puts and can be globally programmed as either push-pull or open-drain. low-emi output buffers can be globally pro- grammed by the software. note: port 1 is not available on the devices in the 28-pin pack- age, and p01m register must set bit d4,d3 as 00 . low- emi mode is not supported on the emulator for port1. pcon register d4 must be 1 . port 1 may be placed under handshake control. in this con- figuration, port 3, lines p33 and p34 are used as the hand- shake controls rdy1 and da v1 (ready and data avail- able). memory locations greater than the internal rom address are referenced through port 1, except for z86c46. to interface external memory, port 1 must be programmed for the multiplexed address/data mode. if more than 256 external locations are required, port 0 outputs the additional lines. port 1 can be placed in the high-impedance state along with port 0, as , ds , and r/w , allowing the z8 to share common resources in multiprocessor and dma applications. figure 13. port 1 con?guration open drain oe out in 1.5 2.3 hysteresis @ v cc = 5.0v pad auto latch (mask option) r 500 k port 1 (i/o or ad7?d0) handshake controls dav1 and rdy1 (p33 and p34) z8 8 pull-up transistor enable (mask option)
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 25 port 2 (p27Cp20). port 2 is an 8-bit, bidirectional, cmos- compatible i/o port. these eight i/o lines are configured under software control as an input or output, independently. port 2 is always available for i/o operation. the input buff- ers are schmitt-triggered. bits programmed as outputs may be globally programmed as either push-pull or open-drain. low-emi output buffers can be globally programmed by the software. port 2 may be placed under handshake control. in this hand- shake mode, port 3 lines p31 and p36 are used as the hand- shake controls lines da v2 and rdy2 . the handshake signal assignment for port 3 lines p31 and p36 is dictated by the di- rection (input or output) assigned to bit 7, port 2 (figure 14). figure 14. port 2 con?guration open drain oe out in 1.5 2.3 hysteresis @ v cc = 5.0v. pad auto latch (mask option) port 2 (i/o) handshake controls z8 r 500 k dav2 and rdy2 (p31 and p36) pull-up transistor enable (mask option)
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 26 p r e l i m i n a r y ds007601-z8x0499 pin functions (continued) port 3 (p37Cp30). port 3 is an 8-bit, cmos-compatible port, with four fixed inputs ( p33Cp30 ) and four fixed out- puts ( p34Cp37 ). it is configured under software control for input/output, counter/timers, interrupt, port handshake, and data memory functions. port 3, bit 0 input is schmitt- triggered, and pins p31 , p32 , and p33 are standard cmos inputs (no auto latches). pins p34 , p35 , p36 , p37 are push- pull output lines. low-emi output buffers can be globally programmed by the software. two onboard comparators can process analog signals on p31 and p32 with reference to the voltage on p33 . the an- alog function is enabled by programming port 3 mode reg- ister ( p3m bit 1 ). for interrupt functions, port 3, bit 0 and pin 3 are falling edge interrupt inputs. p31 and p32 are pro- grammable as rising, falling, or both edge triggered inter- rupts ( irq register bits 6 and 7 ). p33 is the comparator ref- erence voltage input when in analog mode. access to counter/timers 1 is made through p31 ( t in ) and p36 ( t out ). handshake lines for ports 0, 1, and 2 are available on p31 through p36 . port 3 also provides the following control functions: hand- shake for ports 0, 1, and 2 ( da v and rdy ); four external interrupt request signals ( irq3Cirq0 ); timer input and out- put signals ( t in and t out ); data memory select ( dm , see table 10 and figure 15). p34 output can be software-programmed to function as a data memory select ( dm ). the port 3 mode register ( p3m ) bit d3 , d4 selects this function. when accessing external data memory, the p34 goes active low; when accessing external program memory, the p34 goes high. an onboard uart (asci) can be enabled by software by setting the re and te bits of the asci control register a ( cntla ). when enabled, p30 is the receive input and p37 is the transmit output. comparator inputs and outputs. port 3, pins p31 and p32 each feature a comparator front end. the comparator reference voltage, pin p33 , is common to both comparators. in analog mode, the p31 and p32 are the positive inputs to the comparators and p33 is the reference voltage supplied to both comparators. in digital mode, pin p33 can be used as a p33 register input or irq1 source. p34 and p37 outputs the comparator outputs by software-programming the pcon register bit d0 to 1 (see figure 16). note: the user must add a two- nop delay after selecting the p3m bit d1 to 1 before the comparator output is valid. irq0 , irq1 , and irq2 should be cleared in the irq reg- ister when the comparator is enabled or disabled. table 10. port 3 pin assignments pin i/o ctc1 analog int. p0 hs p1 hs p2 hs ext uart p30 in irq3 rx p31 in t in an1 irq2 d/r p32 in an2 irq0 d/r p33 in ref irq1 d/r p34 out an1Cout r/d dm p35 out r/d p36 out t out r/d p37 out an2Cout tx notes: hs = handshake signals d = da v r = rdy
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 27 figure 15. port 3 con?guration d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) from stop-mode recovery source 1 = analog 0 = digital irq2, t in , p31 data latch irq0, p32 data latch irq1, p33 data latch dig. an. auto latch (mask option) p30 data latch irq3 port 3 (i/o or control) z8 + + p30 r 500k p30 p31 p32 p33 p34 p35 p37 p36
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 28 p r e l i m i n a r y ds007601-z8x0499 pin functions (continued) auto latch. the auto latch places valid cmos levels on all cmos inputs (except p33Cp31 ) that are not externally driven. whether this level is 0 or 1 cannot be determined. a valid cmos level, rather than a floating node, reduces excessive supply current flow in the input buffer. auto latches are available on port 0, port 1, port 2, and p30 . there are no auto latches on p31 , p32 , and p33 . note: deletion of all port auto latches is available as a rom mask option. the auto latch delete option is selected by the customer when the rom code is submitted. reset (input, active low). initializes the mcu. reset is accomplished either through power-on reset, watch-dog timer reset, stop-mode recovery, or external reset. during power-on reset and watch-dog reset, the internally-gen- erated reset is driving the reset pin low for the por time. any devices driving the reset line must be open-drain to avoid damage from a possible conflict during reset con- ditions. reset depends on oscillator operation to achieve full reset conditions, except for conditions wherein a wdt reset is permanently enabled. pull-up is provided internally. note: the reset pin is not available on devices in the 28-pin package. after the por time, reset is a schmitt-triggered input. during the reset cycle, ds is held active low while as cycles at a rate of t p c/2 . program execution begins at lo- cation 000ch , after the reset is released. for power-on reset, the reset output time is t por ms. when program execution begins, as and ds toggles only for external memory accesses. the z8 does not reset wdtmr , smr , p2m , pcon , and p3m registers on a stop- mode recovery operation or from a wdt reset out of stop mode. figure 16. port 3 con?guration p34 out p31 + ref (p33) p34 pad p37 out p32 + ref (p33) 0 p34, p37 standard output 1 p34, p37 comparator output pcon d0 p37 pad
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 29 functional description the z8 mcu incorporates the following special functions to enhance the standard z8 ? architecture to provide the user with increased design flexibility. reset. the device is reset in one of the following condi- tions: ? power-on reset ? watch-dog timer ? stop-mode recovery source ? external reset ? low voltage recovery auto power-on reset circuitry is built into the z8, elimi- nating the requirement for an external reset circuit to reset upon power-up. the internal pull-up resistor is on the reset pin, so a pull-up resistor is not required; however, in a high- emi (noisy) environment, it is recommended that a small value pull-up resistor be used. note: the reset pin is not available on devices in the 28-pin package. program memory. the first 12 bytes of program memory are reserved for the interrupt vectors. these locations con- tain six 16-bit vectors that correspond to the six available interrupts. for rom mode, address 12 to address 65535 (c36/c46)/ 32767 (c35/c45)/ 16383 (c34/c44) consists of on-chip mask-programmed rom. the z86c44/c45 can access external program and data memory from addresses 16384/32768 to 65535. the 65535 (c36/c46)/ 32767 (c35/c45)/ 16383 (c34/c44) program memory is mask programmable. a rom protect feature prevents dumping of the rom con- tents by inhibiting execution of ldc , ldci , lde , and ldei instructions to program memory in external program mode . rom look-up tables can be used with this feature. the rom protect option is mask-programmable, to be se- lected by the customer when the rom code is submitted. data memory ( dm ). the romless version can address up to 64 kb of external data memory. external data memory may be included with, or separated from, the external pro- gram memory space. dm , an optional i/o function that can be programmed to appear on pin p34 , is used to distinguish between data and program memory space (figure 18). the state of the dm signal is controlled by the type of instruction being executed. an ldc op code references program ( dm inactive) memory, and an lde instruction references data ( dm active low) memory. the user must configure port 3 mode register ( p3m ) bits d3 and d4 for this mode. this feature is not usable for devices in 28-pin package. when used in rom mode, the z86c46 cannot access any external data memory. the z86c44/c45 can access exter- figure 17. program memory map for z86c34/35/44/45 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 16383/32767 external/internal rom and ram 65535 16382/32766
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 30 p r e l i m i n a r y ds007601-z8x0499 functional description (continued) nal program and data memory from addresses 16384 / 32768 to 65535 . expanded register file (erf). the z8 register file is ex- panded to allow for additional system control registers, and for mapping of additional peripheral devices along with i/o ports into the register address area. the z8 register address space r0 through r15 is implemented as 16 groups of 16 registers per group (figure 19). these register groups are known as the expanded register file ( erf ). bits 7C4 of reg- ister rp select the working register group. bits 3C0 of reg- ister rp select the expanded register group. three system configuration registers reside in the expanded register file at bank f ( pcon , smr , wdtmr ). the rest of the expand- ed register is not physically implemented, and is open for future expansion. figure 18. data memory map 65535 16384/32768 0 external data memory not addressable 16383/32767 rom mode 65535 0 external data memory romless mode
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 31 register file. the register file consists of four i/o port reg- isters, 236 general-purpose registers and 15 control and sta- tus registers ( r0Cr3 , r4Cr239 and r240Cr255 , respective- ly), plus three system configuration registers in the expanded register group. the instructions access registers directly or indirectly through an 8-bit address field. as a re- sult, a short, 4-bit register address can use the register pointer (figure 20). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 figure 19. expanded register file architecture 7 6543210 w orking register group pointer expanded register group pointer %ff %fo %7f %0f %00 z8 reg. file register pointer % ff % fe % fd % fc % fb % fa % f9 % f8 % f7 % f6 % f5 % f4 % f3 % f2 % f1 % f0 spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr 0 u 0 0 u 0 0 1 u u u u 0 % (f) 0f % (f) 0e % (f) 0d % (f) 0c % (f) 0b % (f) 0a % (f) 09 % (f) 08 % (f) 07 % (f) 06 % (f) 05 % (f) 04 % (f) 03 % (f) 02 % (f) 01 % (f) 00 wdtmr smr 0 u u 0 u 1 0 1 u u u u 0 0 u u 0 u 0 0 1 u u u u 0 0 u u 0 u 0 0 1 u u u u 0 0 u u 0 u 1 0 1 u u u u 0 0 u u 0 u 1 0 1 u u u u 0 0 u u 0 u 0 0 1 u u 0 u 0 0 u u 0 u 1 0 1 0 u 0 u 0 uuu0 1 1 0 1 0010 00 0 0 1111uuuu uuuuuuuu uuuuuuuu uuuuuuuu register expanded reg. group (f) reset condition register expanded reg. group(0) reset condition register z8 standard control registers reset condition % (0) 03 p3 % (0) 02 p2 % (0) 01 p1 % (0) 00 p0 d7 d6 d5 d4 d3 d2 d1 d0 reserved * * * ** reserved reserved smr2 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pcon ? * * * 11111110 notes: u = unknown for romless reset condition: ?0110110? *will not be reset with a stop-mode recovery. **will not be reset with a stop-mode recovery, except bit d0. not available on 28-pin packages. x 000000 0 0 000000 0 0 uuuuuu 0 0 * ? x
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 32 p r e l i m i n a r y ds007601-z8x0499 functional description (continued) continuous locations. the register pointer addresses the starting location of the active working register group. figure 20. register pointer d7 d6 d5 d4 d3 d2 d1 d0 expanded register group working register group rp r253 default setting after reset = 00000000 figure 21. register pointerdetail the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register r3 r2 r1 r0 register group 1 register group 0 r15 to r0 register group f r15 to r4 r3 to r0 r15 to r0 ff f0 0f 00 1f 10 2f 20 3f 30 4f 40 5f 50 6f 60 7f 70
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 33 general-purpose registers (gpr). these registers are undefined after the device is powered up. the registers keep their most recent value after any reset , as long as the re- set occurs in the v cc voltage-specified operating range. these do not keep their most recent state from a low volt- age protection ( v lv ) reset if the v cc drops below 1.8v. note: register bank e0Cef is only accessed through working register and indirect addressing modes. ram protect. the upper portion of the rams address spaces %80f to %ef (excluding the control registers) are protected from writing. the ram protect bit option is mask-programmable and is selected by the customer when the rom code is submitted. after the mask option is se- lected, the user activates this feature from the internal rom code to turn off/on the ram protect by loading either a 0 or 1 into the imr register, bit d6 . a 1 in d6 enables ram protect. stack. the z8 internal register file is used for the stack. the 16-bit stack pointer ( r254Cr255 ) is used for the external stack, which can reside anywhere in the data memory for romless mode. an 8-bit stack pointer ( r255 ) is used for the internal stack that resides within the 236 general-pur- pose registers ( r4Cr239 ). stack pointer high (sph) is used as a general-purpose register when using internal stack only. the devices in 28-pin packages use the 8-bit stack pointer ( r255 ) for internal stack only. note: r254 and r255 are set to 00h after any reset or stop- mode recovery. counter/timers. there are two 8-bit programmable counter/timers ( t0Ct1 ), each driven by its own 6-bit pro- grammable prescaler. the t1 prescaler is driven by internal or external clock sources; however, the t0 prescaler is driv- en by the internal clock only (figure 22). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each pres- caler drives its counter, which decrements the value ( 1 to 256 ) that is loaded into the counter. when the counter reaches the end of the count, a timer interrupt request, irq4 ( t0 ) or irq5 ( t1 ), is generated. the counters can be programmed to start , stop , restart to continue , or restart from the initial value. the counters can also be programmed to stop upon reaching 0 (single pass mode) or to automatically reload the initial value and continue counting (moduloCn continuous mode). the counters, but not the prescalers , are read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and is either the internal mi- croprocessor clock divide-by-four, or an external signal in- put through port 3. the timer mode register configures the external timer input ( p31 ) as an external clock, a trigger in- put that can be retriggerable or nonretriggerable, or as a gate input for the internal clock. the counter/timers can be cas- caded by connecting the t0 output to the input of t1 . t in mode is enabled by setting r243 pre1 bit d1 to 0 .
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 34 p r e l i m i n a r y ds007601-z8x0499 functional description (continued) interrupts. the z8 features six different interrupts from six different sources. these interrupts are maskable, prioritized (figure 23) and the six sources are divided as follows: four sources are claimed by port 3 lines p33Cp30 , and two in counter/timers (table 11). the interrupt mask register glo- bally or individually enables or disables the six interrupt re- quests. figure 22. counter/timer block diagram pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter 16 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register 2 clock logic irq4 t p36 irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock d0 (smr) 4 2 osc d1 (smr) out
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 35 when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register. an interrupt ma- chine cycle activates when an interrupt request is granted. this action disables all subsequent interrupts, saves the pro- gram counter and status flags, and then branches to the program memory vector location reserved for that interrupt. all z8 interrupts are vectored through locations in the pro- gram memory. this memory location and the next byte con- tain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled in- terrupt systems, interrupt inputs are masked and the inter- rupt request register is polled to determine which of the in- terrupt requests require service. figure 23. interrupt block diagram table 11. interrupt types, sources, and vectors name source vector location comments irq0 da v0 , irq0 0, 1 external (p32), rise fall edge triggered irq1, irq1 2, 3 external (p33), fall edge triggered irq2 da v2 , irq2, t in 4, 5 external (p31), rise fall edge triggered irq3 uart (asci) 6, 7 external (p30), fall edge triggered irq4 t0 8, 9 internal irq5 t1 10, 11 internal interrupt edge select irq (d6, d7) irq1, 3, 4, 5 irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 irq2
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 36 p r e l i m i n a r y ds007601-z8x0499 functional description (continued) an interrupt resulting from an1 maps to irq2 , and an in- terrupt from an2 maps to irq0 . interrupts irq2 and irq0 may be rising, falling, or both edge-triggered, and are pro- grammable by the user. the software may poll to identify the state of the pin. when in analog mode, the irq1 gener- ates by the stop-mode recovery source selected by smr reg. bits d4 , d3 , d2 , or smr2 d1 or d0 . programming bits for the interrupt edge select are located in the irq register ( r250 ), bits d7 and d6 . the configura- tion is indicated in table 12. clock. the z8 on-chip oscillator features a high-gain, par- allel-resonant amplifier for connection to a crystal, lc , rc , ceramic resonator, or any suitable external clock source ( xtal1 = input , xtal2 = output ). the crystal should be at-cut, 16 mhz maximum, with a series resistance ( rs ) of less than or equal to 100 ohms when counting from 1 mhz to 16 mhz. the crystal should be connected across xtal1 and xtal2 using the vendors recommended capacitor values from each pin directly to the device ground pin to reduce ground- noise injection into the oscillator. the rc oscillator option is mask-programmable on the z8 and is selected by the cus- tomer at the time when the rom code is submitted. notes: the rc option is available up to 8 mhz. the rc oscillator configuration must be an external resistor connected from xtal1 to xtal2 , with a frequency- setting capacitor from xtal1 to ground (figure 24). for better noise immunity, the capacitors should be tied directly to the device ground pin ( v ss ). table 12. irq register irq interrupt edge d7 d6 p31 p32 00ff 01fr 10rf 1 1 r/f r/f notes: f = falling edge r = rising edge
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 37 power-on-reset (por). a timer circuit clocked by a ded- icated on-board rc oscillator is used for the power-on re- set ( por ) timer function. the por time allows v cc and the oscillator circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: 1. power fail to power ok status. 2. stop-mode recovery (if d5 of smr = 1 ). 3. wdt time-out. the por time is specified as t por . bit 5 of the stop-mode register determines whether the por timer is bypassed af- ter stop-mode recovery (typical for external clock, rc / lc oscillators). halt. halt turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external inter- rupts irq0 , irq1 , irq2 , and irq3 remain active. the de- vices are recovered by interrupts and are either externally or internally generated. an interrupt request must be en- abled and executed to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt . in order to enter stop (or halt ) mode, it is necessary to first flush the instruction pipeline to avoid suspending ex- ecution in mid-instruction. therefore, the user must execute a nop (op code = ffh ) immediately before the appropriate sleep instruction. for example: stop. this instruction turns off the internal clock and ex- ternal crystal oscillation. it also reduces the standby current to 10 a or less. the stop mode is terminated by a reset only, either by wdt time-out, por , smr recovery, or ex- ternal reset. as a result, the processor restarts the applica- tion program at address 000ch . a wdt time-out in stop mode affects all registers the same as if a stop-mode re- covery occurred via a selected stop-mode recovery source except that the por delay is enabled even if the delay is se- lected for disable. note: if a permanent wdt is selected, the wdt runs in all modes and cannot be stopped or disabled if the onboard rc oscillator is selected to drive the wdt . port configuration register (pcon). the pcon regis- ter configures the ports individually; comparator output on port 3, open-drain on port 0 and port 1, low emi on ports figure 24. oscillator con?guration xtal1 xtal2 c1 c2 c1 c2 c1 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 47 pf typ * f = 8 mhz lc c1, c2 = 22 pf l = 130 uh * f = 3 mhz * rc @ 5v v (typ) c1 = 33 pf * r = 1k * f = 6 mhz * external clock lr *preliminary value including pin parasitics **device ground pin v ** ss v ** ss v ** ss v ** ss v ** ss cc ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 38 p r e l i m i n a r y ds007601-z8x0499 functional description (continued) 0, 1, 2, and 3, and low-emi oscillator. the pcon register is located in the expanded register file at bank f, location 00h (figure 25). comparator output port 3 (d0). bit 0 controls the com- parator use in port 3. a 1 in this location brings the com- parator outputs to p34 and p37 , and a 0 releases the port to its standard i/o configuration. the default value is 0 . port 1 open-drain (d1). port 1 can be configured as an open-drain by resetting this bit ( d1 = 0 ) or configured as push-pull active by setting this bit ( d1 = 1 ). the default val- ue is 1 . the user must set d1 = 1 for devices in 28-pin pack- ages. port 0 open-drain (d2). port 0 can be configured as an open-drain by resetting this bit ( d2 = 0 ) or configured as push-pull active by setting this bit ( d2 = 1 ). the default val- ue is 1 . low-emi port 0 (d3). port 0 can be configured as a low- emi port by resetting this bit ( d3 = 0 ) or configured as a standard port by setting this bit ( d3 = 1 ). the default value is 1 . low-emi port 1 (d4). port 1 can be configured as a low- emi port by resetting this bit ( d4 = 0 ) or configured as a standard port by setting this bit ( d4 = 1 ). the default value is 1 . the user must set d4 = 1 for devices in 28-pin packages. note: for emulator, this bit must be set to 1 . low-emi port 2 (d5). port 2 can be configured as a low- emi port by resetting this bit ( d5 = 0 ) or configured as a standard port by setting this bit ( d5 = 1 ). the default value is 1 . low-emi port 3 (d6). port 3 can be configured as a low- emi port by resetting this bit ( d6 = 0 ) or configured as a standard port by setting this bit ( d6 = 1 ). the default value is 1 . low-emi osc (d7). this bit of the pcon register con- trols the low-emi noise oscillator. a 1 in this location con- figures the oscillator, ds , as and r/w with standard drive, while a 0 configures the oscillator, ds , as and r/w with low noise drive. the low-emi mode reduces the drive of the oscillator (osc). the default value is 1 . note: maximum external clock frequency of 4 mhz when run- ning in the low-emi oscillator mode. low-emi emission. the z8 can be programmed to operate in a low-emi emission mode in the pcon register. the os- cillator and all i/o ports can be programmed as low-emi emission mode independently. use of this feature results in: ? the pre-drivers slew rate reduced to 10 ns (typical) ? low-emi output drivers exhibit resistance of 200 ohms (typical) ? low-emi oscillator ? internal sclk/tclk = xtal operation limited to a maximum of 4 mhzC250 ns cycle time, when low emi oscillator is selected and system clock ( sclk = xtal , smr register bit d1 = 1 ) stop-mode recovery register (smr). this register se- lects the clock divide value and determines the mode of stop-mode recovery (figures 26 and 27). all bits are write only , except bit 7 , which is read only . bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level is required from the re- covery source. bit 5 controls the reset delay after recovery. bits 2, 3, and 4, or the smr register, specify the source of the stop-mode recovery signal. bits 0 and 1 determine the time-out period of the wdt . the smr is located in bank f of the expanded register group at address 0bh . figure 25. port con?guration register (pcon) (write only) 0 port 0 open drain 1 port 0 push-pull active* d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output 0 port 0 low emi 1 port 0 standard* 0 port 2 low emi 1 port 2 standard* low emi oscillator 0 low emi 1 standard* 0 port 3 low emi 1 port 3 standard* *default setting after reset must be set to one for devices in 28-pin packages 0 port 1 open drain 1 port 1 push-pull active* ? 0 port 1 low emi 1 port 1 standard* ? ?
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 39 sclk/tclk divide-by-16 select (d0). d0 of the smr controls a divide-by-16 prescaler of sclk/tclk . the pur- pose of this control is to selectively reduce device power consumption during normal processor execution ( sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). this bit is reset to d0 = 0 after a stop-mode recovery. external clock divide-by-two (d1). this bit can elimi- nate the oscillator divide-by-two circuitry. when this bit is 0, the system clock ( sclk ) and timer clock ( tclk ) are equal to the external clock frequency divided by 2. the sclk/tclk is equal to the external clock frequency when this bit is set ( d1 = 1 ). using this bit together with d7 of pcon further helps lower emi (that is, d7 ( pcon ) = 0, d1 (smr) = 1 ). the default setting is 0 . maximum external clock frequency is 4 mhz when smr bit d1 = 1 where sclk/tclk = xtal . stop-mode recovery source (d2, d3, and d4). these three bits of the smr specify the wake-up source of the stop recovery (figure 28 and table 13). when the stop- mode recovery sources are selected in this register, then smr2 register bits d0 , d1 must be set to 0 . note: if the port 2 pin is configured as an output, this output level is read by the smr circuitry. figure 26. stop-mode recovery register (write only except bit d7, which is read only) figure 27. stop-mode recovery register 2 (0f) dh: write only d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0b sclk/tclk divide-by-16 0 off * * 1 on stop-mode recovery source 000 por only and/or external reset* 001 p30 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on* stop recovery level 0 low* 1 high stop flag (read only) 0 por* 1 stop recovery note: not used in conjunction with smr2 source * default setting after reset. * * default setting after reset and stop-mode recovery. external clock divide by 2 0 sclk/tclk =xtal/2* 1 sclk/tclk =xtal d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) dh note: not used in conjunction with smr source stop-mode recovery source 2 00 por only* 01 and p20,p21,p22,p23 10 and p20,p21,p22,p23,p24, p25,p26,p27 reserved (must be 0)
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 40 p r e l i m i n a r y ds007601-z8x0499 functional description (continued) stop-mode recovery delay select (d5). this bit, if high, enables the t por reset delay after stop-mode re- covery. the default configuration of this bit is 1 . if the fast wake up is selected, the stop-mode recovery source must be kept active for at least 5 tpc. stop-mode recovery edge select (d6). a 1 in this bit position indicates that a high level on any one of the recov- ery sources wakes the z8 from stop mode. a 0 indicates low-level recovery. the default is 0 on por (figure 28). this bit is used for either smr or smr2 . cold or warm start (d7). this bit is set by the device upon entering stop mode. a 0 in this bit (cold) indicates that the device resets by por / wdt reset . a 1 in this bit (warm) indicates that the device awakens by a stop-mode recovery source. note: if the port 2 pin is configured as an output, this output level is read by the smr2 circuitry. figure 28. stop-mode recovery source p30 p31 p32 p33 p27 stop-mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m) to p33 data latch and irq1 to por reset smr smr smr d4 d3 d2 0 0 1 0 1 0 0 1 1 d4 d3 d2 1 0 0 d4 d3 d2 1 0 1 mux smr smr d4 d3 d2 1 1 0 d4 d3 d2 1 1 1 p20 p23 p20 p27 smr2 smr2 d1 d0 1 1 d1 d0 1 1 p20 p23 p20 p27 smr d4 d3 d2 0 0 0 v smr2 d1 d0 0 0 dd v dd table 13. stop-mode recovery source smr:432 d4 d3 d2 operation description of action 0 0 0 por and/or external reset recovery 0 0 1 p30 transition 0 1 0 p31 transition (not in analog mode) 0 1 1 p32 transition (not in analog mode) 1 0 0 p33 transition (not in analog mode) 1 0 1 p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 41 stop-mode recovery register 2 (smr2). this register contains additional stop-mode recovery sources. when the stop-mode recovery sources are selected in this reg- ister then smr register. bits d2 , d3 , and d4 must be 0 . watch-dog timer mode register (wdtmr). the wdt is a retriggerable one-shot timer that resets the z8 if it reach- es its terminal count. the wdt is initially enabled by exe- cuting the wdt instruction and refreshed on subsequent ex- ecutions of the wdt instruction. the wdt circuit is driven by an onboard rc oscillator or external oscillator from the xtal1 pin. the por clock source is selected with bit 4 of the wdt register (figure 29). wdt instruction affects the z (zero), s (sign), and v (over- flow) flags. the wdtmr must be written to within 64 in- ternal system clocks. after that, the wdtmr is write -pro- tected. note: wdt time-out while in stop mode does not reset smr , pcon , wdtmr , p2m , p3m , ports 2 & 3 data registers, but the por delay counter is still enabled even though the smr stop delay is disabled. wdt time select. (d0,d1). selects the wdt time period and is configured as indicated in table 15. table 14. stop-mode recovery source smr:10 d1 d0 operation description of action 0 0 por and/or external reset recovery 0 1 logical and of p20 through p23 1 0 logical and of p20 through p27 figure 29. watch-dog timer mode register (write only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap int rc osc external clock 00 3.5 ms 128 tpc 01 * 7 ms?56 tpc 10 14 ms512 tpc 11 56 ms 2048 tpc wdt during halt 0 off 1 on * wdt during stop 0 off 1 on * xtal1/int rc select for wdt 0 on-board rc * 1 xtal reserved (must be 0) * default setting after reset table 15. wdt time select d1 d0 timeout of internal rc osc timeout of system clock 0 0 3.5 ms min 128 sclk 0 1 7 ms min 256 sclk 1 0 14 ms min 512 sclk 1 1 56 ms min 2048 sclk notes: sclk = system bus clock cycle. the default on reset is 7 ms. values provided are for v cc = 5.0v.
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 42 p r e l i m i n a r y ds007601-z8x0499 functional description (continued) wdtmr during halt (d2). this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt . the default is 1 . wdtmr during stop (d3). this bit determines whether or not the wdt is active during stop mode. because xtal clock is stopped during stop mode, the on-board rc must be selected as the clock source to the por counter. a 1 in- dicates active during stop . the default is 1 . note: if permanent wdt is selected, the wdt runs in all modes and can not be stopped or disabled if the on board rc oscillator is selected as the clock source for wdt . clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1 , the internal rc oscillator is bypassed and the por and wdt clock source is driven from the external pin, xtal1 . the default configuration of this bit is 0 which selects the internal rc oscillator. wdtmr register accessibility. the wdtmr register is accessible only during the first 60 internal system clock cy- cles from the execution of the first instruction after power- on reset, watch-dog reset, or stop-mode recovery. af- ter this point, the register cannot be modified by any means, intentional or otherwise. the wdtmr cannot be read and is located in bank f of the expanded register group at ad- dress location 0fh (figure 30). note: the wdt can be permanently enabled (automatically enabled after reset ) through a mask programming op- tion. the option is selected by the customer at the time of rom code submission. in this mode, wdt is always activated when the device comes out of reset . execu- tion of the wdt instruction serves to refresh the wdt time-out period. wdt operation in the halt and stop modes is controlled by wdtmr programming. if this mask option is not selected at the time of rom code sub- mission, the wdt must be activated by the user through the wdt instruction and is always disabled by any reset to the device.
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 43 low voltage protection. an onboard voltage compara- tor checks that v cc is at the required level to ensure correct operation of the device. reset is globally driven if v cc is below the specified voltage (low voltage protection). the minimum operating voltage is varying with the temperature and operating frequency, while the low voltage protection ( v lv ) varies with temperature only. the low voltage protection trip voltage ( v lv ) is less than 3v and more than 1.4v under the following conditions. note: the internal clock frequency relationship to the xtal clock is dependent on smr bit 0 1 setting. the device functions normally at or above 3.0v under all conditions. below 3.0v, the device functions normally until the low voltage protection trip point ( v lv ) is reached, for the temperatures and operating frequencies in case 1 and case 2, above. the device is guaranteed to function normally at supply voltages above the low voltage protection trip point. the actual low voltage protection trip point is a func- tion of temperature and process parameters (figure 36). figure 30. resets and wdt clk 18 clock reset generator reset clear wdt tap select internal rc osc. ck clr 5ms por 5ms 15ms 25ms 100ms 2v operating voltage det. internal reset wdt select (wdtmr) clk source select (wdtmr) xtal v v from stop mode recovery source wdt stop delay select (smr) + 4 clock filter wdt/por counter chain m u x reset dd lv table 16. maximum (v lv ) conditions: case 1: t a = C40oc, +105oc, internal clock frequency equal or less than 4 mhz case 2: t a = C40oc, +85oc, internal clock frequency equal or less than 6 mhz
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 44 p r e l i m i n a r y ds007601-z8x0499 asynchronous serial communications interface (asci) key features of the asci include: ? full-duplex operation ? programmable data format ? 7 or 8 data bits with optional ninth bit for multiprocessor communication ? p30 and p37 can be used as general-purpose i/o as long as the asci channels are disabled ? one or two stop bits ? odd, even or no parity ? programmable interrupt conditions ? four level data/status fifos for the receiver ? receive parity, framing and overrun error detection ? break detection and generation transmit data register. data written to the asci trans- mit data register ( tdr ) is transferred to the transmit shift register( tsr ) as soon as the tsr is empty. data can be written while the tsr is shifting out the previous byte of data, providing double buffering for the transmit data. the tdr is read - and write -accessible. reading from the tdr does not affect the asci data transmit operation cur- rently in progress. transmit shift register. when the asci transmit shift register ( tsr ) receives data from the asci transmit data register, the data is shifted out to the tx ( p37 ) pin. when transmission is completed, the next byte (if available) is au- tomatically loaded from the tdr into the tsr and the next transmission starts. if no data is available for transmission, the tsr idles at a continuous high level. this register is not program-accessible. receive shift register. when the re bit is set in the cntla register, the rx ( p30 ) pin is monitored for a low. one-half bit-time after a low is sensed at rx , the asci samples rx again. if rx goes back to high, the asci ignores the previous low and resumes looking for a new low, but if rx is still low, it considers rx a start bit and proceeds to clock in the data based upon the selected baud rate. the number of data bits, parity, multiprocessor and stop bits are selected by the mod2 , mod1 , mod0 and multiprocessor mode ( mp ) bits in the cntla and cntlb registers. after the data is received, the appropriate mp , parity and one stop bit are checked. data and any errors are clocked into the receive data and status fifo during the stop bit if there is an empty position available. interrupts and re- ceive data register full flag also goes active during this time. if there is no space in the fifo at the time that the rsr attempts to transfer the received data into it, an overrun error occurs. receive data fifo. when a complete incoming data byte is assembled in the rsr , it is automatically transferred to the 4-byte fifo, which serves to reduce the incidence of overrun errors. the top (oldest) character in the fifo (if any) can be read via the receive data register ( rdr ). the next incoming data byte can be shifted into the rsr while the fifo is full, thus providing an additional level of buffering. however, an overrun occurs if the receive fifo is still full when the receiver completes assembly of that character and is ready to transfer it to the fifo. if this sit- uation occurs, the overrun error bit associated with the pre- vious byte in the fifo is set. the latest data byte is not trans- ferred from the shift register to the fifo in this case, and is lost. when an overrun occurs, the receiver does not place any further data in the fifo until the most recent good byte received arrives at the top of the fifo and sets the overrun latch, and software then clears the overrun latch by a write of 0 to the efr bit. assembly of bytes continues in the shift register, but this data is ignored until the byte with the overrun error reaches the top of the fifo and the status is cleared. when a break occurs (defined as a framing error with the data equal to all zeros), the all-zero byte with its associated error bits are transferred to the fifo if it is not full and the break detect bit in the asext register is set. if the fifo is full, an overrun is generated, but the break, framing error and data are not transferred to the fifo. any time a break is detected, the receiver does not receive any more data until the rx pin returns to a high state. if the channel is set in multiprocessor mode and the mpe bit of the cntla register is set to 1 ,then break, errors and data are ignored unless the mp bit in the received character is a 1 . the two conditions listed above could cause the miss- ing of a break condition if the fifo is full and the break occurs or if the mp bit in the transmission is not a one with the conditions specified above. asci status fifo/registers. this fifo contains parity error, framing error, rx overrun, and break status bits as- sociated with each character in the receive data fifo. the status of the oldest character (if any) can be read from the asci status register, which also provides several other, non-fifoed status conditions. the outputs of the error fifo go to the set inputs of soft- ware-accessible error latches in the status register. writing
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 45 a 0 to the efr bit in cntla is the only way to clear these latches. in other words, when an error bit reaches the top of the fifo, it sets an error latch. if the fifo contains more data and the software reads the next byte out of the fifo, the error latch remains set until the software writes a 0 to the efr bit. the error bits are cumulative, so if additional errors are in the fifo they set any unset error latches as they reach the top. baud rate generator. the baud rate generator features two modes. the first provides a dual set of fixed clock di- vide ratios as defined in cntlb . in the second mode, the brg is configured as a sixteen-bit down counter that divides the processor clock by the value in a software accessible, sixteen-bit, time-constant register. as a result, virtually any frequency can be created by appropriately selecting the main processor clock frequency. the brg can also be dis- abled in favor of the sclk . the receiver and transmitter subsequently divide the out- put of the baud rate generator (or the signal from the clk pin) by 1, 16 or 64 under the control of the dr bit in the cntlb register and the x1 bit in the asci extension con- trol register ( asext ). reset. during reset , the asci is forced to the following conditions: ? fifo empty ? all error bits cleared (including those in the fifo) ? receive enable cleared ( cntla bit 6 = 0 ) ? transmit enable cleared ( cntla bit 5 = 0 ) figure 31. asci interface diagram internal address/data bus asci transmit data register asci status fifo/register tdr (bank:ah,addr :01h) asci transmit shift register tsr asci receive data fifo rdr (bank:ah,addr:02h) asci receive shift register rsr asci control register a cntla (bank:ah,addr:03h) asci control register b cntlb (bank:ah,addr:04h) stat (bank:ah,addr:08h) asci extension control reg. asext (bank:ah,addr:05h) asci time constant high asci time constant low astcl (bank:ah,add:06h)r baud rate generator sclk (p37) tx (p30) rx asci control irq3 interrupt request ** ** note: **not program accessible astch (bank:ah,addr:07h)
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 46 p r e l i m i n a r y ds007601-z8x0499 interrupts the asci channel generates one interrupt ( irq3 ) from two sources of interrupts: a receiver and a transmitter. in addi- tion, there are several conditions that may cause these in- terrupts to trigger. figure 32 illustrates the different condi- tions for each interrupt source enabled under program control. figure 32. asci interrupt conditions and sources fifo full overrun error framing error parity error start bit receiver interrupt sources buffer empty transmitter interrupt sources asci interrupt (irq3)
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 47 expanded register group (a) figure 33. expanded register group (a) registers %(a)0d reserved %(a)0c reserved %(a)0e reserved %(a)0f reserved %(a)00 reserved %(a)01 tdr %(a)02 rdr %(a)03 cntla %(a)04 cntlb %(a)05 asext %(a)06 astcl %(a)07 astch %(a)08 stat %(a)09 gen purpose u u u u u u u u 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 u u u u u u u u u u u u u u u u * * * * * * * * * not reset with a stop-mode recovery. %(a)0b reserved %(a)0a reserved b7 b6 b5 b4 b3 b2 b1 b0
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 48 p r e l i m i n a r y ds007601-z8x0499 asci transmit data register (tdr) (%(a)01h: read/write) data written to the asci transmit data register ( tdr ) is transferred to the transmit shift register ( tsr ) as soon as the tsr is empty. the tsr is not not software-accessible. the asci transmitter is double-buffered so data can be written to the tdr while the tsr is shifting out the previous byte. data can be written into and read out of the tdr . when the tdr is read, the data transmit operation is not affected. asci receive data register (rdr) (%(a)02h: read/write) when a complete incoming data byte is assembled in the receive shift register ( rsr ), it is automatically transferred to the highest available location in the receive data fifo. the receive data register ( rdr ) is the highest location in the receive data fifo. the rdrf bit in the stat register is set when one or more bytes is available from the fifo. the fifo status for the character in the rdr is available in the stat register via bits 6 , 5 and 4 . stat should be read before reading the rdr . the data in both fifo loca- tions is popped when the character is read from the rdr . asci control register a (cntla) (%(a)03h: read/write) table 17. tdr register bit functions bit76543210 r transmit data w reset uuuuuuuu table 18. rdr register bit functions bit76543210 r receive data w reset uuuuuuuu table 19. cntla register bit functions bit 7 6 5 4 3 2 1 0 r multiprocessor enable (mpe) receiver enable (re) transmitter enable (te) reserved multiprocessor bit received (mpbr) mod2 mod1 mod0 w error flag receive (efr) mode select reset 0 0 0 1 0 0 0 0
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 49 bit 7 is the multiprocessor enable the asci features a multiprocessor communication mode that utilizes an extra data bit for selective communication when a number of processors share a common serial bus. multiprocessor data format is selected when the mp bit in the corresponding register is set to 1 . if multiprocessor mode is not selected ( mp bit in cntlb = 0 ), multiprocessor enable ( mpe ) has no effect. if multiprocessor mode is se- lected ( mp bit in cntlb = 1 ), mpe enables or disables the wake-up feature as follows. if mpe is set to 1 , only received bytes in which the multiprocessor bit ( mpb ) = 1 are treated as valid data characters and loaded into the receiver fifo with corresponding error flags in the status fifo. bytes with mpb = 0 are ignored by the asci. if mpe is reset to 0 , all bytes are received by the asci, regardless of the state of the mpb data bit. bit 6 is the receiver enable when receiver enable( re ) is set to 1 ,the asci receiver is enabled. when re is reset to 0 , the receiver is disabled and any receive operation in progress is aborted. however, the previous contents of the receiver data and status fifo are not affected. bit 5 is the transmitter enable when transmitter enable( te ) is set to 1 ,the asci trans- mitter is enabled. when te is reset to 0 , the transmitter is disabled and any transmit operation in progress is aborted. however, the previous contents of the transmitter data reg- ister and the tdre flag are not affected. bit 4 is reserved bit 3 is the multiprocessor bit receive (read only) when multiprocessor mode is enabled ( mp in cntlb = 1 ), this bit, when read, contains the value of the mpb bit for the data byte currently available at the receive data reg- ister (the top of the receiver fifo). bit 3 is the error flag reset (write only) when written to 0 , the error flags ( ovrn , fe ; pe in stat and brk in asext ) are cleared to 0 . this command self- resets, and as a result, writing efr to a 1 is not required. bits 2C0 are the asci data format mode 2,1,0 these bits program the asci data format. if mod1 = 1 , parity is checked on received data and a parity bit is appended to the data bits in the transmitted data. parity even/odd ( peo ) in cntlb selects even or odd parity. the asci serial data format is illustrated in figure 34. table 20. format mode control bits bit name function bit = 0 bit = 1 2 mod2 number of data bits 7 8 1 mod1 parity enabled no parity with parity 0 mod0 number of stop bits 1 2 figure 34. asci serial data format 7 or 8 bits data field start parity bit bit 1 or 2 stop bit(s) it
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 50 p r e l i m i n a r y ds007601-z8x0499 asci control register b (cntlb) (%(a)04h: read/write) bit 7 is the multiprocessor bit transmit when multiprocessor format is selected ( mp bit = 1 ), mul- tiprocessor bit transmit ( mpbt ) is used to specify the mpb data bit for transmission. if mpbt = 1 , then a 1 is transmitted in the mpb bit position. if mpbt = 0 , a 0 is transmitted. bit 6 is the multiprocessor mode when multiprocessor mode ( mp ) is set to 1 , the serial data format is configured for multiprocessor mode, adding a bit position whose value is specified in mpbt immediately af- ter the specified number of data bits and preceding the spec- ified number of stop bits. note: the multiprocessor format does not provide parity. the serial data format while in mp mode is illustrated in fig- ure 35. if mp = 0 , the data format is based on mod2C0 in cntla and may include parity. bit 5 is the brg prescaler the prescale bit specifies the baud rate generator prescale factor when using the ss2 C 0 bits to define the asci baud rate ( brg mode = 0 ). writing a 0 to this bit sets the brg prescaler to divide by 10. setting this bit to a 1 sets the brg prescaler to divide by 30. see the baud rate generation summary for more information on setting the asci baud rate. bit 4 is the parity even/odd parity even/odd ( peo ) controls the parity bit transmitted on the serial output and the parity check on the serial input. if peo is cleared to 0 , even parity is transmitted and checked if peo is set to 1 , odd parity is transmitted and checked. bit 3 is the divide ratio the divide ratio bit specifies the divider used to obtain the baud rate from the data sampling clock when using the ss2C0 bits to define the asci baud rate ( brg mode = 0 ). if dr is 0 , then divide-by-16 is used. if dr is set to a 1 , then divide-by-64 is used. see the baud rate generation summary for more information on setting the asci baud rate. table 21. cntlb register bit functions bit 7 6 5 4 3 2 1 0 r multiprocessor bit transmitter (mpbt) multiprocessor mode (mp) parity even/odd (peo) divide ratio (dr) ss2 ss1 ss0 w prescale (pr) clock source and speed reset 0 0 0 0 0 1 1 1 figure 35. mp mode serial data format 7 or 8 bits data field start bit mpb 1 or 2 stop bit(s)
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 51 bit 2,1 are the clock source and speed select when the brg mode bit in the asext register is set to 0 , these 3 bits, along with dr and pr in this register define the asci baud rate. bits 2 , 1 and 0 specify a power-of-two divider of the sclk as defined in table 22. these bits should never be set to all 1 s or erratic results may occur. see the baud rate generation summary for more informa- tion on setting the asci baud rate. dr sampling clock 0 divide by 16 1 divide by 64 table 22. clock source and speed bits ss2 ss1 ss0 divider (div) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 reserved
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 52 p r e l i m i n a r y ds007601-z8x0499 asci extension control register (asext) (%(a)05h: read/write) bit 7 is the rx state (read only) provides the real time state of rx , the channels receive data input pin p30 . bit 6 is reserved when read, this bit reflects the default value 0 . when write , this bit is ignored. bit 5 is reserved when read, this bit reflects the default value 0 . when write , this bit is ignored . bit 4 is the x1 bit clock reservedmust be set to 0 or erratic results may occur. bit 3 is the brg mode when this bit is set to a 1 , the ascis baud rate is set by the 16-bit programmable divider programmed in asci time constant high (asth ) and asci time constant low ( astl ). if this bit is set to a 0 , the baud rate is defined by the pr bit, the dr bit, and the ss2C0 bits in the cntlb reg- ister. in either case, the source for the baud rate generator is the sclk . see the baud rate generation summary for more information on setting the asci baud rate. bit 2 is the rx interrupt on start if software sets this bit to 1 ,a receive interrupt is requested (in a combinatorial fashion) when a start bit is detected on rx . such a receive interrupt is always followed by the setting of rdrf in the middle of the stop bit. this interrupt request must be cleared by writing this bit back to a 0 . writ- ing a 1 to this bit has no effect. one function of this feature is to wake the part from sleep mode when a character ar- rives, so that the asci receives clocking with which to pro- cess the character. another function is to ensure that the as- sociated interrupt service routine is activated in time to sense the setting of rdrf in the status register, and to start a timer for baud rate measurement at that time. bit 1 is the break detect (read only) this status bit is set to a 1 when a break is detected, defined as a framing error with the data bits all equal to 0 . the all- zero byte with its associated error bits are transferred to the fifo if it is not full. if the fifo is full, an overrun is gen- erated, but the break, framing error and data are not trans- ferred to the fifo. any time a break is detected, the receiver do not receive any more data until the rx pin returns to a high state. when set, this bit remains set until it is cleared by writing a 0 to the efr bit in the cntla register. bit 0 is the send break setting this bit to a 1 forces the channels transmitter data output pin, tx , to a low for as long as it remains set. before starting the break, any character(s) in the tsr and in the tdr are completely transmitted. if a character is loaded into the tdr while a break is being generated, that character is held until the break is terminated and transmitted. table 23. asext register bit functions bit76543210 r rx state (rx) reserved reserved reserved (must be 0) brg mode (brgm) rx interrupt on start bit (ris) break detect (bd) send break (sb) w reset p30 0000000
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 53 asci time constant register (astl) (%(a)06h: read/write) asci time constant register (asth) (%(a)07h: read/write) the astl and asth registers are only used when the brg mode bit in the asext register is set to a 1 . these two 8- bit registers form a 16-bit counter with a flip-flop logic cir- cuit ( divide-by-2 ) on the output so that the final brg out- put is symmetrical. the values written to these registers de- termine the time constant from which the baud rate is generated. table 24. astl register bit functions bit76543210 r asci time constant low w reset 11111111 table 25. asth register bit functions bit76543210 r asci time constant high w reset 11111111
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 54 p r e l i m i n a r y ds007601-z8x0499 asci status register (stat) (%(a)08h: read/write) bit 7 is the receive data register full rdrf is set to 1 when the receiver transfers a character from the rsr into an empty rx fifo. note: if a framing or parity error occurs, rdrf is still set and the receive data (which generated the error) is still load- ed into the fifo. when there is more than one character in the fifo, and soft- ware reads a character, rdrf either remains set or is cleared and immediately set again. rdrf is cleared to 0 when the fifo becomes empty after reading the rdr and during power-on reset. bit 6 is the overrun error an overrun occurs if the receive fifo is still full when the receiver completes assembly of a character and is ready to transfer it to the fifo. if this situation occurs, the overrun error bit associated with the previous byte in the fifo is set. in this case, the latest data byte is not transferred from the shift register to the fifo and is lost. when an overrun occurs, the receiver does not place any further data in the fifo until the most recent good byte received (the byte with the associated overrun error bit set) moves to the top of the fifo and sets the overrun latch, and software then clears the overrun latch. assembly of bytes continues in the shift register, but this data is ignored until the byte with the overrun error reaches the top of the fifo and the status is cleared. when set, the bit remains set until it is cleared by writing a 0 to the efr bit in the cntla register. the bit is also cleared during power-on reset. bit 5 is the parity error a parity error is detected when parity generation and check- ing is enabled by the mod1 bit in the cntla register and a character has been assembled in which the parity does not match that specified by the peo bit in cntlb . note: pe is fifoed and the error bit is not actually set until the associated data becomes available for reading in the rdr . when set, the bit remains set until it is cleared by writing a 0 to the eft bit in the cntla register. the bit is cleared at power-on reset. bit 4 is the framing error a framing error is detected when the stop bit of a character is sampled as a 0 (space). like pe , fe is fifoed and the error bit is not actually set until the associated data becomes available for reading in the rdr . when set, the bit remains set until it is cleared by writing a 0 to the efr bit in the cntla register. the bit is cleared at power-on reset. bit 3 is the receiver interrupt enable rie should be set to a 1 to enable asci receive interrupt requests. an interrupt ( irq3 ) is generated when rdrf (bit 7 of the stat register) is a 1 . a receive interrupt is also generated if this bit is set to a 1 , bit 2 of the asext register ( rx interrupt on the start bit) is set to a 1 , and a start bit is detected by the receiver. table 26. asci status register (stat) bit76543210 r receive data register full (rdrf) overrun error (oe) parity error (pe) framing error (fe) receiver interrupt enable (rie) reserved transmit data register empty tdre) transmitter interrupt enable (tie) w reset 00000000
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 55 bit 2 is reserved when read, this bit reflects the default value 0 . when write , this bit is ignored. bit 1 is the transmit data register empty tdre = 1 indicates that the transmit data register ( tdr ) is empty and that the next data byte to be transmitted can be written into the tdr . tdre is cleared to 0 after the byte is written to tdr , until the asci transfers the byte from the tdr to the transmit shift register ( tsr ), and then tdre is again set to 1 . tdre is set to 1 at power-on reset. bit 0 is the transmit interrupt enable tie should be set to a 1 to enable asci transmit interrupt requests. an interrupt ( irq3 ) is generated when tdre (bit 1 of the stat register) is a 1 . tie is cleared to 0 at power- on reset. an anomaly exists that requires setting of the rie bit to al- low the generation of transmit interrupts. if rie is not set, transmit interrupts are not generated, even if tie is set. see precautions . baud rate generation summary the application can select between one of two baud rate generators for the asci. if the brg mode bit in the asext register is set to a 0, the ss2,1,0 bits, the dr, bit and the pr bit in cntlb are used to select the baud rate. if the brg mode bit is set to a 1, the astl and asth registers are used to select the baud rate. the following formulas are used to calculate the baud rate from the two baud rate generators: if brg mode = 0 : where: 1. sclk is the system clock. 2. ps = 1 or 0 and is bit 5 of cntlb . 3. div = 1 , 2 , 4 , 8 , 16 , 32 or 64 as reflected by ss2C0 in cntlb . 4. divide ratio = 16 or 64 , as defined by dr in cntlb . if brg mode = 1 : or where: 1. sclk is the system clock. 2. tc is the 16-bit value programmed into astl and asth . 3. divide ratio = 16 or 64 , as defined by dr in cntlb . 4. baud rate is the desired baud rate. baud rate = sclk (10 + 20 x ps) x div x divide ratio baud rate = sclk (2 x (tc + 2) x divide ratio tc = sclk C 2 2 x baud rate x divide ratio
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 56 p r e l i m i n a r y ds007601-z8x0499 asci status register (stat) (continued) table 27. baud rate list (brg mode = 0) prescaler sampling rate baud rate general divide ratio example baud rate (bps) ps divide ratio dr rate ss2 ss1 ss0 divide ratio sclk = 6.144 mhz sclk = 4.608 mhz sclk = 3.072 mhz 0 sclk 10 016 0 0 0 1 sclk 160 38400 19200 0 0 1 2 sclk 320 19200 9600 0 1 0 4 sclk 640 9600 4800 0 1 1 8 sclk 1280 4800 2400 1 0 0 16 sclk 2560 2400 1200 1 0 1 32 sclk 5120 1200 600 1 1 0 64 sclk 10240 600 300 164 0 0 0 1 sclk 640 9600 4800 0 0 1 2 sclk 1280 4800 2400 0 1 0 4 sclk 2560 2400 1200 0 1 1 8 sclk 5120 1200 600 1 0 0 16 sclk 10240 600 300 1 0 1 32 sclk 20480 300 150 1 1 0 64 sclk 40960 150 75 1 sclk 30 016 0 0 0 1 sclk 480 4800 0 0 1 2 sclk 960 2400 0 1 0 4 sclk 1920 1200 0 1 1 8 sclk 3840 600 1 0 0 16 sclk 7680 300 1 0 1 32 sclk 15360 150 1 1 0 64 sclk 30720 75 164 0 0 0 1 sclk 1920 2400 0 0 1 2 sclk 3840 1200 0 1 0 4 sclk 7680 600 0 1 1 8 sclk 15360 300 1 0 0 16 sclk 30720 150 1 0 1 32 sclk 61440 75 1 1 0 64 sclk 122880 37.5
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 57 low voltage protection figure 36. typical low voltage protection vs. temperature v cc (volts) 3.60 3.20 3.00 2.80 2.60 2.40 -60 -40 -20 0 20 40 60 80 100 120 140 3.80 3.40 temperature (?) v (typical) lv a b a b run/halt mode stop mode
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 58 p r e l i m i n a r y ds007601-z8x0499 mask options below is an example of the rom mask bit option selection for this product. rom protect. selecting the disable rom protect op- tion read s the software program that is in the program memory using zilogs internal factory test mode. how- ever, none of the standard methods for reading or verifying the code in the microcontroller uses an eprom program- mer. with this option disabled, zilog is able to fully test the rom memory and provides its standard warranty for the part. selecting the enable rom protect option ne- gates the possibility of reading the code out of the part using a tester, programmer, or any other standard method. zilog will be unable to test the rom memory at any time prior to customer delivery. the rom protect option bit only affects the ability to read the code and does not affect the operation of the part in an application. if the rom protect option is disabled, zilog tests the part for rom fallout and parts which fail are not shipped to the customer. when the rom protect option is enabled, zilog cannot perform these tests on the rom. when rom protect is enabled, except for the im- proper transfer of the code by zilog, all rom memory software errors shall be the responsibility of the buyer and zilog shall have no obligation to repair or replace product containing software errors. selecting the enable rom protect option waives all warranties of zilog, ex- pressed or implied, on microcontrollers containing rom failures including, but not limited to, the implied warranty of merchantability and fitness for a particular purpose. ram protect. selecting the disable ram protect op- tion does not affect the ram memory. ram memory op- erates as defined in this product specification for all address locations. selecting the enable ram protect option, allows protection (under software control) of a portion of the rams address space from being read or written. system clock source. selecting the rc oscillator enable option, configures the oscillator circuit on the mi- crocontroller to work with an external rc circuit. selecting the crystal/other clock source option configures the oscillator circuit to work with an external crystal, ce- ramic resonator, or lc oscillator. oscillator operational mode. selecting the normal high frequency operation enabled option en- ables the part to operate using a standard crystal or resona- tor, but it does not operate using a 32-khz crystal. selecting the 32-khz operation enabled option enables the mi- crocontroller to work with a 32-khz crystal and an external feedback resistorthese must be supplied between the xtal1 and xtal2 pins. (if rc oscillator enabled is selected in the system clock source option, this option defaults to the normal high frequency op- eration enabled bit.) wdt mode. selecting the wdt enabled by soft- ware only option operates the watch dog timer (wdt) when turned on under software control. selecting the wdt enabled automatically after reset option starts the wdt automatically at reset .there is no way to dis- able or stop this mode, making it necessary in the code to periodically clear the wdt to prevent it from resetting the microcontroller. if the wdt enabled automatical- ly after reset option and the wdt driven by sys- tem clock option (if offered) are selected, the wdt nev- options option selections rom protect disable rom protect enable rom protect ram protect disable ram protect enable ram protect system clock source rc oscillator enable crystal/other clock source oscillator operational mode normal high-frequency operation enabled 32-khz crystal operation enabled (limits high-frequency operation) wdt mode wdt enabled by software only wdt enabled automatically after reset auto latch mode disable auto latches enable auto latches port 0 pull-ups disable pull-ups enable pull-ups port 1 pull-ups disable pull-ups enable pull-ups port 2 pull-ups disable pull-ups enable pull-ups
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 59 er operates in stop mode, and cannot be enabled, by any means, to operate in stop mode. auto latch mode. selecting the disable autolatch- es option disables the autolatches on the port pins. these pins will float rather than be pulled to a valid cmos level when they are inputs and not connected to an external sig- nal. selecting the enable autolatches option enables the autolatches on the port pins and pulls the pins to a valid cmos level when they are not connected to an external sig- nal. port 0 pull-ups. selecting disable pull-ups disables the input pull-up circuitry on all port 0 pins. selecting en- able pull-ups enables the input pull-up circuitry on all port 0 pins. this option bit does not affect any of the other port pins on the part. port 1 pull-ups. selecting disable pull-ups disables the input pull-up circuitry on all port 1 pins. selecting en- able pull-ups enables the input pull-up circuitry on all port 1 pins. this option bit does not affect any of the other port pins on the part. port 2 pull-ups. selecting disable pull-ups disables the input pull-up circuitry on all port 2 pins. selecting en- able pull-ups enables the input pull-up circuitry on all port 2 pins. this option bit does not affect any of the other port pins on the part.
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 60 p r e l i m i n a r y ds007601-z8x0499 expanded register file control registers figure 37. stop-mode recovery register (write only, except bit d7, which is read only) figure 38. stop-mode recovery register2 d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0b sclk/tclk divide-by-16 0 off * * 1 on stop-mode recovery source 000 por only and/or external reset* 001 p30 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on* stop recovery level 0 low* 1 high stop flag (read only) 0 por* 1 stop recovery note: not used in conjunction with smr2 source * default setting after reset. * * default setting after reset and stop-mode recovery. external clock divide by 2 0 sclk/tclk =xtal/2* 1 sclk/tclk =xtal d7 d6 d5 d4 d3 d2 d1 d0 smr2 (0f) dh note: not used in conjunction with smr source stop-mode recovery source 2 00 por only* 01 and p20,p21,p22,p23 10 and p20,p21,p22,p23,p24, p25,p26,p27 reserved (must be 0) figure 39. watch-dog timer mode register (write only) d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap int rc osc system clock 00 3.5 ms 128 sclk 01 10 ms 256 sclk 10 14 ms 512 sclk 11 56 ms 2048 sclk wdt during halt 0 off 1 on wdt during stop 0 off 1 on xtal1/int rc select for wdt 0 on-board rc 1 xtal reserved (must be 0) * default setting after reset * * * *
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 61 z8 control registers figure 40. port con?guration register (pcon) (write only) figure 41. timer mode register (f1 h : read/write) 0 port 0 open drain 1 port 0 push-pull active* d7 d6 d5 d4 d3 d2 d1 d0 pcon (fh) 00h comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output 0 port 0 low emi 1 port 0 standard* 0 port 2 low emi 1 port 2 standard* low emi oscillator 0 low emi 1 standard* 0 port 3 low emi 1 port 3 standard* *default setting after reset must be set to one for devices in 28-pin packages 0 port 1 open drain 1 port 1 push-pull active* ? 0 port 1 low emi 1 port 1 standard* ? ? d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count 1 enable t0 count 0 no function 1 load t0 0 no function 1 load t1 0 disable t1 count 1 enable t1 count tin modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) tout modes 00 not used 01 t0 out 10 t1 out 11 internal clock out r241 tmr figure 42. counter/timer 1 register (f2 h : read/write) figure 43. prescaler 1 register (f3 h : write only) figure 44. counter/timer 0 register (f4 h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 t initial value (when written) (range: 1-256 decimal 01-00 hex) t current value (when read) 1 1 r242 t1 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n clock source 1 t1internal 0 t1external timing input (tin) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 d7 d6 d5 d4 d3 d2 d1 d0 t0 initial value (when written) (range: 1-256 decimal 01-00 hex) t0 current value (when read) r244 t0
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 62 p r e l i m i n a r y ds007601-z8x0499 z8 control registers (continued) figure 45. prescaler 0 register (f5 h : write only) figure 46. port 2 mode register (f6 h : write only) figure 47. port 3 mode register (f7 h : write only) 0 t0 single pass 1 t0 modulo n d7 d6 d5 d4 d3 d2 d1 d0 count mode reserved (must be 0) prescaler modulo (range: 1-64 decimal 01-00 hex) r245 pre0 d7 d6 d5 d4 d3 d2 d1 d0 p20 - p27 i/o definition 0 defines bit as output 1 defines bit as input r246 p2m d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 pull-ups open drain 1 port 2 push-pull active 0 p31, p32 digital mode 1 p31, p32 analog mode 0 p32 = input p35 = output 1 p32 = dav0 /rdy0 p35 = rdy0/dav0 00 p33 = input p34 = output 01 p33 = input 10 p34 = dm p34 = rdy1/dav1 0 p31 = input (t in ) p36 = output (t out ) 1 p31 = dav2 /rdy2 p36 = rdy2/dav2 0 p30 = input ? reserved (must be 0) 11 p33 = dav0 /rdy0 p37 = output figure 48. port 0 and 1 mode register (f8 h : write only) figure 49. interrupt priority register (f9 h : write only) d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p00?03 mode 00 output 01 input 1x a11?8 stack selection 0 external 1 internal p10 - p17 mode 00 byte output 01 byte input 10 ad7 - ad0 11 high-impedance ad7?d0, as, ds, r/w, a11?8, a15?12, if selected p04?07 mode 00 output 01 input 1x a15?12 external memory timing 0 normal 1 extended for 28 pin device, the user must set: d2=1 d3=0 d4=0 ? ? ? d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 reserved (must be 0) r249 ipr
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 63 figure 50. interrupt request register (fa h : read/write) figure 51. interrupt mask register (fb h : read/write) figure 52. flag register (fc h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 r250 irq inter edge p31 p32 = 00 p31 p32 - = 01 p31 - p32 = 10 p31 - p32 - = 11 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = p30 input irq4 = t0 irq5 = t1 d7 d6 d5 d4 d3 d2 d1 d0 1 enables ram protect * 1 enables irq0-irq5 (d0 = irq0) 1 enables interrupts r251 imr * this option must be selected when rom code is submitted for rom masking, otherwise this control bit is disabled permanently. d7 d6 d5 d4 d3 d2 d1 d0 r252 flags user flag f1 * user flag f2 * half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag * not affected by reset figure 53. register pointer (fd h : read/write) figure 54. stack pointer high (fe h : read/write) figure 55. stack pointer low (ff h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 r253 rp expanded register file working register pointer d7 d6 d5 d4 d3 d2 d1 d0 stack pointer upper byte (sp8 - sp15) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp0 - sp7) r255 spl
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 64 p r e l i m i n a r y ds007601-z8x0499 package information figure 56. 28-pin dip package diagram figure 57. 28-pin soic package diagram
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 65 figure 58. 28-pin plcc package diagram figure 59. 40-pin dip package diagram
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 66 p r e l i m i n a r y ds007601-z8x0499 figure 60. 44-pin plcc package diagram figure 61. 44-pin qfp package diagram
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 67 ordering information for fast results, contact your local zilog sales office for assistance in ordering the part required. z86c34 standard temperature extended temperature 28-pin dip 28-pin soic 28-pin plcc 28-pin dip 28-pin soic 28-pin plcc z86c3416psc z86c3416ssc z86c3416vsc z86c3416pec z86c3416sec z86c3416vec Z86C35 standard temperature extended temperature 28-pin dip 28-pin soic 28-pin plcc 28-pin dip 28-pin soic 28-pin plcc Z86C3516psc Z86C3516ssc Z86C3516vsc Z86C3516pec Z86C3516sec Z86C3516vec z86c36 standard temperature extended temperature 28-pin dip 28-pin soic 28-pin plcc 28-pin dip 28-pin soic 28-pin plcc z86c3616psc z86c3616ssc z86c3616vsc z86c3616pec z86c3616sec z86c3616vec z86c44 standard temperature extended temperature 40-pin dip 44-pin plcc 44-pin qfp 40-pin dip 44-pin plcc 44-pin qfp z86c4416psc z86c4416vsc z86c4416fsc z86c4416pec z86c4416vec z86c4416fec z86c45 standard temperature extended temperature 40-pin dip 44-pin plcc 44-pin qfp 40-pin dip 44-pin plcc 44-pin qfp z86c4516psc z86c4516vsc z86c4516fsc z86c4516pec z86c4516vec z86c4516fec z86c46 standard temperature extended temperature 40-pin dip 44-pin plcc 44-pin qfp 40-pin dip 44-pin plcc 44-pin qfp z86c4616psc z86c4616vsc z86c4616fsc z86c4616pec z86c4616vec z86c4616fec
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 68 p r e l i m i n a r y ds007601-z8x0499 precautions (continued) precautions 1. enabling the transmit interrupt (bit 0 in the asci stat register) does not make the device ready for transmitter-related interrupts. the receiver interrupt (bit 3 in the asci stat register) must also be enabled. workaround : for transmit interrupts to be generated, the rie bit must also be set. when irq3 is generated, the software should check the stat register for details on the interrupt source. 2. when using the device in full-duplex mode under in- terrupts (both transmit and receive interrupts enabled), a small window exists where a transmit or receive in- terrupt may be lost. this situation occurs when an in- terrupt is generated by one side (either the transmitter or receiver) and, before the interrupt is serviced, an- other interrupt is generated by the other side. the sec- ond interrupt may be lost. workaround : the only workaround is not to use transmitter interrupts when using the asci in full- duplex mode. use the transmitter in polled mode and the receiver in interrupt mode for full duplex operation. in half-duplex operation, this anomaly does not create a problem.
z86c34/c35/c36/c44/c45/c46 zilog cmos z8? mcus with asci uart ds007601-z8x0499 p r e l i m i n a r y 69 codes for fast results, contact your local zilog sales office for assistance in ordering the part required. example: the z86c36 is a 16-mhz plcc, 0oc to 70oc, with plastic standard flow. pre-characterization product the product represented by this document is newly introduced and zilog has not completed the full characterization of the product. the document states what zilog knows about this product at this time, but additional features or nonconformance with some aspects of the document may be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery may be uncertain at times, due to start-up yield issues. ?1999 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. zilog, inc. 910 east hamilton avenue, suite 110 campbell, ca 95008 telephone (408) 558-8500 fax (408) 558-8300 internet: http://www.zilog.com preferred package p = plastic dip v = plastic chip carrier longer lead time f = plastic quad flat pack s = small outline integrated chip preferred temperature s = 0c to +70c longer lead time e = C40c to +105c speed 16 = 16 mhz environmental c = plastic standard z zilog pre?x 86c36 product number 16 speed p package s temperature c environmental flow
z86c34/c35/c36/c44/c45/c46 cmos z8? mcus with asci uart zilog 70 p r e l i m i n a r y ds007601-z8x0499

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